R&D Senior Engineer/ Manager/ Senior Manager

4 - 9 Years
Bengaluru, Chennai

Job Description


Hi

Good day to you...!

Openings with US based Semiconductor MNCs please go through the Job Descriptions & let me know your interest for the same.

Company/ies Name will be Disclosed With your Interest

Work Location : Bangalore & Hyderabad

Here attaching the JD for your reference

Responsibilities:

  • Design DFT logic including inserting MEMBIST, boundary scan, scan, and at speed ATPG (Transition Delay Fault Testing).
  • Work with digital design and backend teams on DFT architecture/partitioning.
  • Run RTL, gate, and gate with SDF simulations to confirm correct functionality of DFT logic.
  • Generate ATPG vectors, bring-up and debug patterns, resolve test pattern and coverage issues, support test engineering and operations through qualification, burn-in, and production
  • Support failure analysis and fault isolation of pattern failures

Qualifications:
  • Must have experience inserting, testing, and using DFT logic functions (JTAG, BIST, mBIST, scan, boundary scan, ATPG) on multiple chips that have been through tape-out and product ramp.
  • Must have experience with logic design, especially involving multiple clock domains.
  • Must have some experience with Perl or other similar scripting languages.
  • Experience with silicon lab bring-up.
  • Experience operating a tester to debug patterns is a plus.
  • Experience with physical design tools (such as PrimeTime) is a plus.
  • Must be able to work within a small team on multiple tasks.
  • Clear written and verbal communication skills

Education and Experience:
  • BS (MS preferred) in Electrical Engineering, Computer Science, or related field
  • Minimum 3+ years applicable experience

Note : If you are not Interested, Kindly refer any of your Friends/colleagues with 3+ yrs

Thanks & Regards
Bala Koppu
Technical Recruiter
bala@cambio.co.in

Salary: Not Disclosed by Recruiter

Industry:Semiconductors / Electronics

Functional Area:IT Software - Embedded, EDA, VLSI, ASIC, Chip Design

Role Category:Programming & Design

Role:Team Lead/Technical Lead

Keyskills

Desired Candidate Profile

Please refer to the Job description above

Education-

UG:B.Tech/B.E. - Any Specialization

PG:M.Tech - Any Specialization, MS/M.Sc(Science) - Any Specialization

Company Profile

Cambio Consulting India Pvt Ltd

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Contact Company:Cambio Consulting India Pvt Ltd

Email :bala@cambio.co.in