Design and validation of various DFT features such as Scan/ATPG, JTAG, iJTAG, etc. for Intel's leading-edge SoC designs and Post Silicon Support. Define test architecture, Coverage analysis and enhancement, work with FABs/manufacturing teams on DPPM reduction, yield debug support.
Supports silicon bring up of test patterns. Performs diagnosis of test patterns on silicon and optimizes test time. Responsible for leading the team technically and growing the team to the next level.
Salary: Not Disclosed by Recruiter
Role Category:Programming & Design
Role:Team Lead/Technical Lead
Desired Candidate Profile
Cambio Consulting India Pvt Ltd