Should have worked on several full chip designs both flat and hierarchical designs
Strong knowledge in RTL to Netlist handoff to Physical design team
Experience in low power/ multi voltage design and understanding of UPF is preferred
Knowledge on Cadence based flows is preferred
Knowledge on DFT and Physical design is preferred
Synopsys/ Cadence tool experience is preferred.
Good communication skills.
Salary: INR 3,50,000 - 8,50,000 PA.
Industry:Semiconductors / Electronics
Functional Area:IT Software - Embedded, EDA, VLSI, ASIC, Chip Design
Role Category:Programming & Design
Role:Team Lead/Technical Lead
Desired Candidate Profile
Cambio Consulting India Pvt Ltd
Recruiter Name:Sheshagiri Rao
Contact Company:Cambio Consulting India Pvt Ltd