STA Synthesis 3-9 years

3 - 8 Years
Bengaluru, Hyderabad

Job Description

STA Synthesis 3-9 years

Lead STA Synthesis
The position is responsible for full chip level timing constraints (STA) , power aware physical synthesis and formal verification
Formal verification for RTL 2 gates and gates2gates
UPF 2.0 based power aware equivalence checking using Conformal.
Debugging PA-FV failures
Conformal ECO for doing complex functional ECOs.
Low power synthesis on smaller blocks and subsystems using DC/Genus
Physical Aware synthesis
Minimum Qualifications
3-9 years Hardware Engineering experience or related work experience.
Candidate should be expert in debugging STA timing constraints
Should be able to handle conformal ECO generation independently.
Good know how of power aware synthesis and physical aware synthesis.
Perl/tcl scripting will a plus
Keywords
Synthesis, STA, SoC, Conformal, Timing Constriants etc..

Salary: Not Disclosed by Recruiter

Industry:Semiconductors / Electronics

Functional Area:IT Software - Embedded, EDA, VLSI, ASIC, Chip Design

Role Category:Programming & Design

Role:System Analyst

Keyskills

Desired Candidate Profile

Please refer to the Job description above

Company Profile

Cambio Consulting India Pvt Ltd

Shiva
9848331769
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Recruiter Name:Sheshagiri Rao

Contact Company:Cambio Consulting India Pvt Ltd