RTl Designer

5 - 10 Years
Bengaluru, Chennai, Delhi, Hyderabad, Pune, Noida

Job Description

RTL Synthesis 3-12 years
Job description:
The candidate will be part of the design team and his responsibilities will include but will not be limited to:
-Running low power synthesis on RTL
-Generating and defining timing constraints. Debug of constraint failures and power intent related constraint failure
-Doing ECOs in netlist -Formal equivalence between RTL and netlist and netlist/netlist
-Debug of synthesis failures
-Low power checks and other netlist quality checks
-Timing analysis and signoff
-RTL release flow checks lint, elab, clock domain crossing etc. debug of issues and fixes needed

Salary: Not Disclosed by Recruiter

Industry:Semiconductors / Electronics

Functional Area:IT Software - Embedded, EDA, VLSI, ASIC, Chip Design

Role Category:Programming & Design

Role:Testing Engineer

Employment Type:Permanent Job, Full Time

Keyskills

Desired Candidate Profile

Please refer to the Job description above

Education-

UG:B.Tech/B.E. - Any Specialization

PG:MS/M.Sc(Science) - Any Specialization, M.Tech - Any Specialization, PG Diploma - Any Specialization

Company Profile

Cambio Consulting India Pvt Ltd

A Networking & Product development
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Contact Company:Cambio Consulting India Pvt Ltd