Design RTL-SOC-IP-STA-Synthesis Engineer ( Experience 3 9 yrs

3 - 8 Years
Bengaluru, Hyderabad

Job Description

Design RTL-SOC-IP-STA-Synthesis Engineer ( Experience 3 9 yrs )

MULTIPLE Positions ranging from Junior to Sr. Staff Engineer.
Sound experience in RTL Design is REQUIRED ranging from 3 to 9 Years.
The open Design positions in different teams are:-

1.CPU Design (CPUSS)/ ASIC Design / SOC Design / GPU Design
2.Component Design / IP Design
3.Logic Design / Micro-Architecture
5.Modem Design
6.Low-Power Design And many more...

The selected candidate will have the following responsibilities:
Block level RTL (Verilog or System Verilog) design from micro-architecture level specifications.
Implementation of Low power logic, targeting power, performance, area, and timing goals.
Linting, CDC, LEC and preferably Low Power check tools to implement design and check design quality Work with Design Verification team on block and top-level functional/gate level verification and code coverage, including Power aware debug.

Salary: Not Disclosed by Recruiter

Industry:Semiconductors / Electronics

Functional Area:Engineering Design, R&D

Role Category:Engineering Design

Role:Design Engineer


Desired Candidate Profile

Please refer to the Job description above

Company Profile

Cambio Consulting India Pvt Ltd

View Contact Details+

Recruiter Name:Shiva

Contact Company:Cambio Consulting India Pvt Ltd