Openings with US based Semiconductor MNCs please go through the Job Descriptions & let me know your interest for the same.
Synthesis & STA Lead/Engineer 3-12 years
- The position is responsible for full chip level timing constraints (STA) , power aware physical synthesis and formal verificationFormal verification for RTL 2 gates and gates2gates
- UPF 2.0 based power aware equivalence checking using Conformal.
- Debugging PA-FV failures
- Conformal ECO for doing complex functional ECOs.
- Low power synthesis on smaller blocks and subsystems using DC/Genus
- Physical Aware synthesis
- 3-12 years Hardware Engineering experience or related work experience.
- Candidate should be expert in debugging STA timing constraints
- Should be able to handle conformal ECO generation independently.
- Good know how of power aware synthesis and physical aware synthesis.
- Perl/tcl scripting will a plus
Note : If you are not Interested/Not Open for Job Options, Kindly refer any of your Friends/colleagues with 3+ yrs
Salary: Not Disclosed by Recruiter
Industry:Semiconductors / Electronics
Functional Area:IT Software - Embedded, EDA, VLSI, ASIC, Chip Design
Role Category:Programming & Design
Role:Team Lead/Technical Lead
Desired Candidate Profile
UG:B.Tech/B.E. - Any Specialization
PG:MS/M.Sc(Science) - Any Specialization, M.Tech - Any Specialization
Cambio Consulting India Pvt Ltd
Contact Company:Cambio Consulting India Pvt Ltd